1. Field of the Invention
The present invention relates to package structures, and, more particularly, to a low-profile package structure, a fabricating method thereof, and a thin-profiled package-on-package device having the package structure.
2. Description of Related Art
Along with the rapid development of electronic industry, electronic product are becoming low-profiled and compact-sized. Their specifications need to comply with the regulations set by Joint Electronic Device Engineering Council (JEDEC), so how they are packaged is quite important. For example, a dynamic random access memory (DRAM) chip is developed toward 40 nm or less, and the chip size thus becomes smaller and smaller. However, the area occupied by a packaged unit is not changed after packaging, so the ball pitch for a package to be mounted on a printed circuit board (PCB) still has to remain as small as 0.8 mm, in order to comply with the JEDEC standard. Accordingly, a fan-out wafer level chip scale package (Fan-Out WLP) is available, wherein a double-data-rate three synchronous dynamic random access memory (DDR3 SDRAM) is a specification for computer memory, and is generally packaged in a Window BGA form.
Referring to FIG. 1, a cross-sectional diagram of a package structure 1 according to the prior art is provided. The package structure 1 includes a packaging substrate 10 having an opening 100, and a semiconductor chip 11 with an active surface 11a disposed on a bottom surface 10b of the packaging substrate 10. The semiconductor chip 11 covers one end of the opening 100. Electrode pads 110 of the semiconductor chip 11 are exposed from the opening 100. The electrode pads 110 are electrically connected to bonding pads 101 on a top surface 10a of the packaging substrate 10 by gold wires 12. A protective material 14 is filled in the opening 100 to cover the gold wires 12. An encapsulant 13 is formed on the bottom surface 10b of the packaging substrate 10 and covers an inactive surface 11b and a lateral surface of the semiconductor chip 11. The top surface 10a of the packaging substrate 10 has ball-implanting pads 102 thereon, and solder balls 16 are disposed on the ball-implanting pads 102 for electrically connecting the semiconductor chip 11 to a circuit board (not shown). The package structure 1 (including the solder balls 16) has an overall height equal to 1.1-1.2 mm.
Since the gold wires 12 are used in the prior art, the package structure 1 cannot have a low profile.
Besides, the length of the gold wires 12 results in adverse effect on electric performance (e.g., the capacitance and inductance) of the package structure 1, so the package structure 1 cannot meet the requirements for a wide bandwidth memory.
The package structure 1 having the gold wires 12 is high in fabrication cost.
Therefore, how to overcome the problems in the prior art is becoming one of the most popular issues in the art.